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So far, almost all submissions on this site are ones that target "standard" computers, namely devices that execute code in a typically linear fashion, with a standard variety of inputs/outputs (standard in/out/err, file, rendering a window). However, this seems to make programs targeting hardware other than standard computers a grey area due to lack of precedent, performance considerations (where solutions must take only a reasonable amount of time), and different input/output considerations than standard programs running on computers with operating systems.

This highly upvoted answer to "What are programming languages?" describes the requirements for the language to be used, and in turn, the platform. The hardware+language easily fits a transformational model, handles representations of integers and collections thereof, can add numbers, and can perform primality checks. The language is text-based so byte-counting considerations have already been resolved by precedent with other text-based languages.

However, I'd still like a second opinion from the community on whether these languages/hardware devices are appropriate when not explicitly disallowed by a question, and what is allowed for inputs/outputs (e.g. serial transcievers, clocking data in/out through pins in serial/parallel fashion, reading/writing block RAMs (precedent), or if in a simulator, through standard file/stream IO).

Additionally, in cases where execution is either timed as a limit or as the sorting criterion for answers, I'm assuming that the requirement is that the design meets timing for some frequency F_max on a commercially-produced FPGA available at the time of writing the challenge, and then the solution time is simply the time it takes for the output to be provided at that frequency F_max. Is that a correct way to go about that?

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  • \$\begingroup\$ The timing part for fastest code challenges would be tricky. We'd either need challenge authors to specify a frequency that the solution will use for timing, or have a default (or both). \$\endgroup\$ – Mego Jul 28 '16 at 20:00
  • \$\begingroup\$ @Mego Why not simply use the F_max possible for any given design on a commercially-available FPGA? It is dependent on the design complexity (especially levels of logic and routing complexity), and thus I cannot create a solution and run it at some absurd clock speed it would not be able to achieve on physical hardware. \$\endgroup\$ – hexafraction Jul 28 '16 at 20:08
  • \$\begingroup\$ Because that maximum frequency will go up over time. We would want comparisons across challenges in the language meaningful, which won't happen unless they are compared at the same frequency. \$\endgroup\$ – Mego Jul 28 '16 at 20:09
  • \$\begingroup\$ @Mego At the same time, standardizing the clock frequency removes the incentive for highly optimized logic and routing, as well as opening up a question of how to handle an inefficient design that can't meet timing (especially when after improvements over time it suddenly begins to start meeting timing at the standardized frequency). Perhaps the rule that a language/version must exist before the contest can be extended so that the silicon device used for the timing score for that design must exist before the question is posted? \$\endgroup\$ – hexafraction Jul 28 '16 at 20:12
  • \$\begingroup\$ Fastest code challenges are usually timed on a specific machine belonging to the challenge author, so a language that requires different hardware is ruled out by that, unless the challenge makes allowances to remedy that. \$\endgroup\$ – trichoplax Jul 31 '16 at 22:45
  • \$\begingroup\$ @trichoplax If there is a specific machine requirement, then could a simulator (with appropriate test bench) be used then? \$\endgroup\$ – hexafraction Jul 31 '16 at 23:33
  • \$\begingroup\$ That sounds like a good solution. Sounds in keeping with our "must have a working compiler/interpreter" rule. \$\endgroup\$ – trichoplax Jul 31 '16 at 23:56
  • \$\begingroup\$ @trichoplax How does that work if the compiler/interpreter is an extremely large (>6GB) proprietary freeware installation? \$\endgroup\$ – hexafraction Aug 1 '16 at 0:05
  • \$\begingroup\$ As long as the simulator is free (as in beer) to use without a time limit (see this thread for the relevant discussion), then there shouldn't be any issues. \$\endgroup\$ – Mego Aug 1 '16 at 0:43
  • \$\begingroup\$ @Mego Understood, thanks. If the simulator has an artificial 100kloc limit then would submissions under 100k lines of code still be acceptable? \$\endgroup\$ – hexafraction Aug 1 '16 at 0:45
  • \$\begingroup\$ Certainly. However, if your submission surpasses that limit, another interpreter will need to be found/created for it to be a valid submission. \$\endgroup\$ – Mego Aug 1 '16 at 0:47
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Yes, such languages are valid, with the following caveats:

  • A simulator must be available that can run the code. In order for the submission to be competitive, along with any other challenge-specific requirements, the simulator must have existed prior to the posting of the challenge.
  • challenges pose a bit of a problem, since the speed of execution is directly linked to the clock speed. We will need a default clock speed for such challenges, with the option for challenge authors to override this default if they so please. I propose the semi-arbitrary speed of 300 MHz, which is based on current commercial FPGA's clock speeds.
  • I/O also poses a bit of a problem, but that's just because we haven't had many proposals on the I/O methods meta post. Surely, any of the allowed methods for assembly language (such as input and output through a specified memory block) would also be acceptable for HDLs.
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  • \$\begingroup\$ Thanks! Unfortunately, it seems that 300MHz is too high and poses no incentive to optimize levels of logic for timing (which would be in the spirit of a fastest-code challenge). I'm thinking that it would be more appropriate to select some FPGA from each of the major manufacturers/software tools and use that device's logic/speed for the frequency determination rather than set 300MHz. Additionally, as for simulation, how will the character count of a testbench that feeds the inputs to the FPGA design affect scoring? (such a testbench, of course, would not be used with a physical FPGA). \$\endgroup\$ – hexafraction Aug 1 '16 at 18:02
  • \$\begingroup\$ If there's a simulator available then surely that can be used for timing fastest-code? \$\endgroup\$ – Peter Taylor Aug 1 '16 at 20:26
  • \$\begingroup\$ @PeterTaylor Presumably the simulator would have an adjustable clock rate. Different clock rates would not only affect the timing of the solution, but also the design of the FPGA circuit. \$\endgroup\$ – Mego Aug 1 '16 at 20:26
  • \$\begingroup\$ @PeterTaylor Additionally, simulators are really slow compared to actual FPGA circuits. On a complex design reaching 100MHz on an older FPGA (spartan-3e) the simulator may only be able to do hundreds of KHz to 1MHz depending on whether it compiles/interprets and other factors. Additionally some simulators don't actually have frequency-dependent behaviour--they will simulate actions on a given edge and immediately jump to the next edge until told to stop by a)running out of code generating clocks b)hitting $finish( c)Simulating as much (design, not wall) time as requested by user. \$\endgroup\$ – hexafraction Aug 2 '16 at 11:29

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