# Can We Make 0-NAND OR Gates in [logic-gates] Challenges?

Some challenges require you to use only NAND gates to solve a problem. Usually, constructing an OR gate from NAND gates requires 3 NAND gates. However, an OR gate can also be constructed using 0 NAND gates, by simply joining 2 pieces of wire together:

A---\
---Output
B---/


Is joining 2 pieces of wire allowed or are we going to have to use NAND gates to make OR gates?

# It depends on the question.

is a tag for challenges about logic gates. It doesn't, and shouldn't, come with special rules like this.

If the person that poses the challenge wants that to be permitted they can say so. We leave it up to them to decide what they think makes the best challenge. Even if we agreed that there was a case which would be better in almost all scenarios, adding hidden rules on the meta to every question using a tag is still a bad idea.

The person posting a challenge should be responsible for making it clear and self contained. If they haven't addressed this point in the question body it is probably not allowed, but it could also just be the question is unclear. That should be addressed on a question by question basis.

# No

Disclaimer: I am inexperienced with this challenge type.

I feel that it makes more sense to by default disallow it and force OR gates to be explicitly constructed. This could of course be vetoed on a by-challenge basis.

# Yes

I don't have much experience with this challenge type, but I see no reason why not. The only things used would be wire and NAND gates, both allowed by the challenge. Of course a challenge could expressly forbid this for more difficulty if it wanted to.